Every integrated circuit (IC) manufactured today relies upon an elaborate system of metallized interconnects to couple together the various devices which are fabricated in the semiconductor substrate. The technology for forming these metallized interconnects is extremely sophisticated and well-understood. Usually, aluminum or some other metal, is deposited and then patterned to form interconnect paths along the surface of the substrate material. In most processes, an insulative layer is then deposited over this first metal (metal 1) layer. Via openings are then etched through the insulative layer and a second metalization layer is deposited. The second metal (metal 2) layer covers the insulative layer and fills the via openings down to the metal 1 layer. The purpose of the dielectric layer, of course, is to act as an insulator between the metal 1 and metal 2 interconnects.
In many ICs, the interlayer dielectric comprises a chemical vapor deposition (CVD) of silicon dioxide. The silicon dioxide layer is normally formed to a thickness of approximately one micron. The underlying metal 1 layer is also formed to a thickness of approximately one micron. This silicon dioxide layer covers the metal 1 interconnects conformably such that the upper surface of the silicon dioxide layer is characterized by a series of non-planar steps which correspond in height and width to the underlying metal 1 lines.
These step height variations in the upper surface of the interlayer dielectric have several undesirable features. First, a non-planar dielectric surface interferes with the optical resolution of subsequent photolithographic processing steps. This makes it extremely difficult to print high resolution lines. A second problem involves the step coverage of the metal 2 layer over the interlayer dielectric. If the step height is too large there is a serious danger that open circuits will be formed in the metal 2 layer.
To combat these problems, various techniques have been developed in an attempt to better planarize the upper surface of the interlayer dielectric. One approach employs abrasive polishing to remove the protruding steps along the upper surface of the dielectric. According to this method, the silicon substrate is placed facedown on a table coated with an abrasive material. Both the wafer and the table are then rotated relative to each other in an abrasive fashion to remove the protruding portions. This abrasive polishing process continues until the upper surface of the dielectric layer is largely flattened. In certain processes, polishing is performed at an elevated temperature (i.e., higher than room or ambient temperatures).
While the abrasive polishing process greatly improves the overall flatness of the dielectric surface, there are certain drawbacks. Instead of producing a completely planar dielectric upper surface, the amount of polishing that takes place in a given location is highly dependent on the underlying metal topology. In those areas where a narrow interconnect line (on the order of 10 microns) runs across a wide field region (on the order of 1-10 mm), the interlayer dielectric can become dramatically thinned as compared to those regions where the metal width is considerably wider (e.g., 1-10 mm). In some instances, thinning of the dielectric can reach a point where the underlying metal 1 trace becomes exposed. Most often, the thickness variation problem results in a via depth differential which makes via etching and via filling (i.e., with metal 2) more difficult. Having a dielectric thickness which is dependent upon topology also hinders circuit design and simulation efforts.
As will be seen, the present invention provides a polishing process for improving the degree of planarization attainable in a dielectric layer formed over a semiconductor substrate.